參數(shù)資料
型號(hào)： MT90520
廠商： Zarlink Semiconductor Inc.
英文描述： 8-Port Primary Rate Circuit Emulation AAL1 SAR
中文描述： 8端口基本速率電路仿真AAL1特區(qū)
文件頁(yè)數(shù)： 143/180頁(yè)
文件大?。?/td> 1736K
代理商： MT90520
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MT90520
Data Sheet
143
Zarlink Semiconductor Inc.
TDM_PULSE_
SEL
5
R/W
TDM Frame Pulse Selection. (Applies only to SDT mode.)
‘0’ = STiMF pin is a frame pulse.
‘1’ = STiMF pin is a multiframe pulse.
In Backplane SDT mode, this bit must cleared.
TDM_PULSE_
POL
6
R/W
TDM Frame Pulse Polarity. (Applies only to SDT mode.)
In Generic mode:
‘0’ = Negative polarity.
‘1’ = Positive polarity.
In ST-BUS mode, this bit must be cleared.
TDM_CLK_POL
7
R/W
Segmentation TDM Input Clock Polarity.
‘0’ = TDM data is sampled on the rising edge.
‘1’ = TDM data is sampled on the falling edge.
In ST-BUS SDT mode, this bit must be set.
TDM_CLK_RATE
8
R/W
TDM Clock Rate.
‘0’ = TDM clock is 1.544 MHz.
‘1’ = TDM clock is 2.048 MHz or 4.096 MHz.
TDM_LINK_TYPE
9
R/W
TDM Link Type.
‘0’ = E1 link.
‘1’ = DS1 link.
INT_LOS_
ENABLE
10
R/W
Internal LOS Enable (Applies only to UDT mode).
‘0’ = Internal version of LOS disabled.
‘1’ = Internal version of LOS enabled.
If this bit is set, the occurrence of an LOS event on the port will be propagated throughout
the device, possibly influencing the signals output on PRI_REF, PRI_LOS, and the port’s
SToCLK.
This bit must be set if TDM_LOS_CLK (bit<1>) is set.
TDM_CLK_MODE
11
R/W
TDM Clocking Mode. (Applies only to SDT mode; must be cleared in UDT mode.)
‘0’ = Independent mode (Independent clocks and frame pulses)
‘1’ = Backplane mode (Common clock and frame pulse)
TDM_BUS_
MODE
12
R/W
TDM Bus Mode (Applies only to SDT mode; must be cleared in UDT mode.)
‘0’ = Generic.
‘1’ = ST-BUS. (The clock is 4.096 MHz.)
TDM_DATA_
FORMAT
14:13
R/W
TDM Data Mode.
“00” = No cells generated from this port.
“01” = UDT mode
“10” = SDT mode.
“11” = SDT mode with N>46. This mode should be used when any VC associated with this
port has more than 46 channels.
TDM_LOW_
LATENCY_LPBK
15
R/W
Low latency loopback.
‘0’ = Normal operation.
‘1’ = Loopback data from DSTi to DSTo.
Note 1:
If this bit is set, data from DSTi is output on DSTo, regardless of the value of the
TDM_REASS_PORT_CONTROL bit in TDM Control Register 3 (i.e., even if the port is
apparently inactive, loopback data will be output on DSTo).
Note 2:
To use low-latency loopback, the clock edge used to sample the incoming TDM
data (determined by TDM_CLK_POL in this register) must be opposite to the clock edge
used to drive the outgoing TDM data (determined by TDM_REASS_CLK_POL, set at
6204h).
Note 3:
The delay through the device in low latency loopback mode is approximately 2
TDM clock cycles.
Address: 6200 + p*10 (Hex)
Label: TDM1_Pp (where p represents the port number)
Reset Value: 0000 (Hex)
Label
Bit
Position
Type
Description
Table 82 - TDM Control Register 1 (one per port)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT90520AG 制造商:Microsemi Corporation 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays
MT90520AG2 制造商:Microsemi Corporation 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays
MT90528 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR
MT90528AG 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR
MT90528AG2 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR
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