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參數(shù)資料
| 型號(hào)： | MT90520 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | 8-Port Primary Rate Circuit Emulation AAL1 SAR |
| 中文描述： | 8端口基本速率電路仿真AAL1特區(qū) |
| 文件頁(yè)數(shù)： | 100/180頁(yè) |
| 文件大?。?/td> | 1736K |
| 代理商： | MT90520 |
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MT90520
Data Sheet
100
Zarlink Semiconductor Inc.
SDT Operation
In some cases, the STiCLK/C4M/C2M/PLLCLK input clock requires modification prior to being used in the RTS
generator circuit described above. The line rate clock (i.e., 2.048 MHz for DS1/E1/backplane) which is input to the
MT90520 represents the rate at which bits are being received on a particular port. In SDT mode, the line rate only
represents the bit rate of a VC if the entire stream (e.g., 32 channels in ST-BUS mode) is transmitted in a single VC.
For all other cases (i.e., for N-channel VCs, where N is less than the maximum number of channels on a port), the
RTS-generating clock must represent the bit rate of a particular VC. This bit rate is determined by the number of
channels transmitted within a VC. Figure 40 below shows the line rate clock being passed through the gapping
divider circuitry to generate a bit-rate clock.
Figure 40 - Gapping Circuitry for SDT Operation
The gapping circuit operates as follows: the line rate clock (STiCLK, C4M/C2M, or PLLCLK) must be equal to a
framed clock rate. For DS1, E1, and backplane modes, this rate must be 2.048 MHz. However, the user must
provide this clock differently, depending on the mode being employed. If the port is operating in
independent
clock
mode, the 2.048 MHz clock is presented on STiCLK and the user should select the port’s STiCLK as the source for
the RTSSEL mux. When operating in
Generic
backplane
mode, the desired 2.048 MHz clock rate is available at
C4M/C2M. Therefore, the user should select C4M/C2M as the source for the RTSSEL mux. When operating in
ST-
BUS
backplane
mode, the C4M/C2M signal has a clock rate of 4.096 MHz. This clock is too high to be the line rate
clock for the port. Therefore, the user must provide an appropriate 2.048 MHz clock on the STiCLK input for the
port. The user must then select the STiCLK input as the source of the RTSSEL mux. This half-rate STiCLK signal
will not be used elsewhere in the port’s circuitry, because the TDM module will use the C4M/C2M clock if it is
programmed in backplane mode. In any case, the signal which is output from the RTSSEL multiplexer is input to the
circuit at “l(fā)ine rate clock”. “N” in the above figure represents the number of channels in the VC (N < 24 for DS1; N <
30 for E1; N < 32 for ST-BUS). Adding the number of channels to the accumulator at the rate of the line rate clock,
the “carry” of the adder provides the desired clock rate. For example, if using a 2.048 MHz line rate with an 18-
channel VC, we want to achieve the following result: carry = 2.048 MHz * (18/32) = 1.152 MHz. Looking at the
hardware implementation, we would see the following:
+
N
accumulator
carry
linerate
framesize
-----------N
×
=
line rate clock
(2.048 MHz
synchronized to mclk)
Note1:
N < 24 for DS1; N < 30 for E1; N < 32 for ST-BUS
Note2:
frame size = 32 for DS1/E1/ST-BUS
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT90520AG | 8-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT9072 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT9072AB | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT9072AV | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT90820 | Large Digital Switch |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90520AG | 制造商:Microsemi Corporation 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays |
| MT90520AG2 | 制造商:Microsemi Corporation 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays |
| MT90528 | 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT90528AG | 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT90528AG2 | 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
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