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參數(shù)資料
| 型號： | MT90520 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | 8-Port Primary Rate Circuit Emulation AAL1 SAR |
| 中文描述： | 8端口基本速率電路仿真AAL1特區(qū) |
| 文件頁數(shù)： | 105/180頁 |
| 文件大?。?/td> | 1736K |
| 代理商： | MT90520 |
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MT90520
Data Sheet
105
Zarlink Semiconductor Inc.
Sub-modes of Operation (PLL_MODE_SEL bits)
Within each mode described above, the PLL has four sub-modes:
Normal sub-mode: The input (be it a clock, RTS nibbles, or phasewords) is used to synchronize the PLL
output clock to the input.
Holdover sub-mode: Either when configured as such by the user (via the PLL_MODE_SEL bits) or when a
port experiences an LOS condition (while operating in UDT mode), the PLL is switched to holdover sub-
mode. When in the holdover state, the PLL ignores the input and holds the output clock at its current
deviation from the center frequency.
Freerun sub-mode: In this sub-mode, a clock rate of 1.544 MHz, 2.048 MHz, or 4.096 MHz is generated. No
input is used and the output frequency is fixed to the nominal center frequency.
CPU sub-mode: In this mode of operation, the offset from the center frequency of the output clocks is
determined by the value written to the per-port Clocking DCO Difference Register by an external CPU. The
value programmed by the CPU is used to set the PLL output frequency directly, instead of using the PLL’s
internal filter output. This mode is intended to put an external CPU into the PLL loop. The CPU can read the
filter output (from the per-port Clocking Phase Accumulator Register), process it, and write the desired factor
to the DCO. This mode of operation might be used if the user wanted to implement a loop filter with a very
large time constant.
More detail regarding how to configure the PLL for the various modes of operation can be found in the register
descriptions for the Clock Management Module, found in Section 6.2.8 on page 136.
4.7.2.8 Frequency Behaviour
The PLL must generate frequencies with an accuracy as stated in Table 20. The accuracy defines the freerun
accuracy and the locking range of the PLL. The accuracy of the master clock (MCLK), which has to be running at
66 MHz, must be incorporated into these figures. A freerun accuracy of approximately 0.1 ppm and a locking range
of approximately 250 ppm has been implemented, thereby allowing 100 ppm MCLK accuracy and a 150 ppm input
clock / RTS nibble range.
Jitter and Wander
The af-vtoa-0078.000 standard with respect to jitter and wander points to several ANSI and ITU-T standards, as
summarized in Table 21. The jitter requirements are met in all clocking modes. The wander requirements may not
(nor need they) be met in adaptive mode.
The standards from Table 21 specify wander/jitter input tolerance and maximum output jitter. For the input wander/
jitter tolerance, the low frequency parts are the largest and are therefore the most important for the PLL
requirements (see Table 22). With a corner frequency larger than 1.2 Hz, the PLL will follow wander below 0.1 Hz.
Clock
Frequency (MHz)
1.544
2.048
4.096
Table 20 - Center Frequency and Accuracy
Accuracy (ppm)
-0.13
0.05
0.05
1 UI (ns)
648
488
244
C1M5 (DS1)
C2M (E1)
C4M
Clock
Jitter
Wander
ANSI T1.403
ITU-T G.824
ITU-T G.823
C1M5 (DS1)
ANSI T1.102
ITU-T G.824
ITU-T G.823
C2M (E1)
Table 21 - Relevant Specifications
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| MT90520AG | 8-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT9072 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT9072AB | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT9072AV | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT90820 | Large Digital Switch |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90520AG | 制造商:Microsemi Corporation 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays |
| MT90520AG2 | 制造商:Microsemi Corporation 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays |
| MT90528 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT90528AG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT90528AG2 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
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