參數(shù)資料
型號: ST72321BM
廠商: 意法半導體
英文描述: 80-PIN 8-BIT MCU WITH 32 TO 60K FLASH/ROM, ADC, FIVE TIMERS, SPI, SCI, I2C INTERFACE(具有ICP,IAP,Nested Interrupt,TLI,ROP的8位MCU)
中文描述: 80引腳8位微控制器32至60,000閃存/ ROM,ADC的,5個定時器,SPI和SCI的I2C接口(具有比較方案,國際檢察官聯(lián)合會,嵌套中斷,中華語文研習所,人事登記的8位微控制器)
文件頁數(shù): 34/178頁
文件大?。?/td> 3121K
代理商: ST72321BM
ST72F321M, ST72321BM
34/178
INTERRUPTS
(Cont’d)
7.3 INTERRUPTS AND LOW POWER MODES
All interrupts allow the processor to exit the WAIT
low power mode. On the contrary, only external
and other specified interrupts allow the processor
to exit from the HALT modes (see column “Exit
from HALT” in “Interrupt Mapping” table). When
several pending interrupts are present while exit-
ing HALT mode, the first one serviced can only be
an interrupt with exit from HALT mode capability
and it is selected through the same decision proc-
ess shown in
Figure 18
.
Note
: If an interrupt, that is not able to Exit from
HALT mode, is pending with the highest priority
when exiting HALT mode, this interrupt is serviced
after the first one serviced.
7.4 CONCURRENT & NESTED MANAGEMENT
The following
Figure 19
and
Figure 20
show two
different interrupt management modes. The first is
called concurrent mode and does not allow an in-
terrupt to be interrupted, unlike the nested mode in
Figure 20
. The interrupt hardware priority is given
in this order from the lowest to the highest: MAIN,
IT4, IT3, IT2, IT1, IT0, TLI. The software priority is
given for each interrupt.
Warning
: A stack overflow may occur without no-
tifying the software of the failure.
Figure 19. Concurrent Interrupt Management
Figure 20. Nested Interrupt Management
MAIN
11 / 10
IT4
IT2
IT1
TRAP
IT1
MAIN
IT0
I1
H
SOFTWARE
PRIORITY
LEVEL
3
3
3
3
3
3/0
3
1 1
1 1
1 1
1 1
1 1
1 1
RIM
I
I
I
T
I
I
IT3
I0
10
U
MAIN
11 / 10
IT2
TRAP
MAIN
IT0
I
I
I
T
I
I
H
3
2
1
3
3
3/0
3
1 1
0 0
0 1
1 1
1 1
1 1
RIM
IT1
IT4
IT4
IT1
IT2
IT3
I1
I0
10
SOFTWARE
PRIORITY
LEVEL
U
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