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參數(shù)資料
| 型號(hào)： | S1C63158D0A010Q |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, FLASH, 4 MHz, MICROCONTROLLER, UUC53 |
| 封裝： | DIE-53 |
| 文件頁(yè)數(shù)： | 148/159頁(yè) |
| 文件大?。?/td> | 1200K |
| 代理商： | S1C63158D0A010Q |
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S1C63808 TECHNICAL MANUAL
EPSON
81
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
Transmit/receive ready (SRDYx) signal
When this serial interface is used in the clock synchronous slave mode (external clock input), an
SRDYx signal is output from the SRDYx terminal to indicate whether or not this serial interface can
transmit/receive to the master side (external serial input/output device).
When positive polarity is selected
The SRDYx signal goes "1" (high level) when this interface enters the transmit or receive enable
(READY) status, and it goes "0" (low level) when the interface is in a BUSY status, such as during
transmit/receive operation.
The SRDYx signal changes "0" to "1" immediately after writing "1" into the transmit control bit
TXTRGx or the receive control bit RXTRGx and it returns to "0" at the point where the first syn-
chronous clock is input (rising edge).
When negative polarity is selected
___________
The SRDYx signal goes "0" (low level) when this interface enters the transmit or receive enable
(READY) status, and it goes "1" (high level) when the interface is in a BUSY status, such as during
transmit/receive operation.
___________
The SRDYx signal changes "1" to "0" immediately after writing "1" into the transmit control bit
TXTRGx or the receive control bit RXTRGx and it returns to "1" at the point where the first syn-
chronous clock is input (falling edge).
When you have set in the master mode, control the transfer by inputting the same signal from the
slave side using the input port or I/O port. At this time, since the SRDYx terminal is not set and
instead P13/P23 functions as the I/O port, you can apply this port for said control.
Timing chart
The timing chart for the clock synchronous system transmission is shown in Figure 4.10.6.4.
SCLKx
TXTRGx (RD)
SCLKx
SOUTx
D0 D1 D2 D3 D4 D5 D6 D7
TXENx
Interrupt
TXTRGx (WR)
()
SCLKx
TXTRGx (RD)
SOUTx
D0 D1D2D3D4D5D6 D7
TXENx
Interrupt
TXTRGx (WR)
SRDYx
SCLKx
SRDYx
()
SCLKx
RXTRGx (RD)
SCLKx
SINx
D0 D1 D2 D3 D4 D5 D6 D7
RXENx
Interrupt
RXTRGx (WR)
TRXDx
7F
1st data
()
SCLKx
RXTRGx (RD)
SINx
D0 D1 D2 D3 D4 D5 D6 D7
RXENx
Interrupt
RXTRGx (WR)
TRXDx
7F
1st data
SRDYx
SCLKx
SRDYx
7F
()
(a) Transmit timing for master mode
(c) Receive timing for master mode
(b) Transmit timing for slave mode
(d) Receive timing for slave mode
Fig. 4.10.6.4 Timing chart (clock synchronous system transmission)
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