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| 型號(hào)： | MC68HC05B16 |
| 廠商： | Motorola, Inc. |
| 元件分類： | DC/DC變換器 |
| 英文描述： | RS-S_D(Z) Series - Econoline Regulated DC-DC Converters; Input Voltage (Vdc): 24V; Output Voltage (Vdc): 15V; Power: 2W; 2:1 and 4:1 Wide Input Voltage Ranges; 1kVDC, 2kVD & 3kVDC Isolation; UL94V-0 Package Material; Continuous Short Circuit Protection; Low Noise; No External Capacitor needed; Efficiency to 83% |
| 中文描述： | 高密度互補(bǔ)金屬氧化物半導(dǎo)體（HCMOS）微機(jī)組 |
| 文件頁數(shù)： | 77/96頁 |
| 文件大?。?/td> | 3045K |
| 代理商： | MC68HC05B16 |
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MC68HC05SR3
Freescale
11-3
ELECTRICAL SPECIFICATIONS
11
Table 11-2 DC Electrical Characteristics for 3V Operation
(VDD=3.0Vdc ±10%, VSS=0Vdc, temperature range=0 to 70°C)
CHARACTERISTICS
SYMBOL
MINIMUM
TYPICAL
MAXIMUM
UNIT
Output voltage
ILOAD = –10A
ILOAD = +10A
VOH
VOL
VDD–0.1
—
0.1
V
Output high voltage (ILOAD=–0.8mA)
All Ports
VOH
VDD–0.3
—
V
Output low voltage (ILOAD=+1.6mA)
All Ports
VOL
—0.1
0.3
V
Output high current
(VOH=1.0V) All ports
IOH
2.7
3.5
4.7
mA
Output low current
(VOL=2.0V) All ports
IOL
3.0
4.0
5.2
mA
Total I/O port current
Either source or sink
IPORT
—
100
—
mA
Input high voltage
PA0-PA7, PB0, PB1, IRQ, RESET, OSC1
VIH
0.7×VDD
—VDD
V
Input low voltage
PA0-PA7, PB0, PB1, IRQ, RESET, OSC1
VIL
VSS
—0.2×VDD
V
Supply current:
Run
Wait
Stop 25°C
0°C to +70°C (Standard)
–40°C to +85°C (Extended)
IDD
—
2.4
0.75
—
3.5
1.5
20
30
40
mA
A
I/O ports high-Z leakage current
PA0-PA7, PB0-PB7, PC0-PC7, PD0-PD7
IIL
——
±10
A
Input current
RESET, IRQ, OSC1
IIN
——
±1
A
Capacitance
Ports (as input or output)
RESET, IRQ, OSC1, OSC2
COUT
CIN
—
12
8
pF
Pull-up resistor
PA0-PA7, PB0-PB7, PC0-PC7, PD0-PD7
RESET, IRQ
RPU
14
85
36
100
50
176
K
Notes:
(1) All values shown reflect average measurements.
(2) Typical values at midpoint of voltage range, 25°C only.
(3) Wait IDD: Only timer system active.
(4) Wait, Stop IDD: All ports configured as inputs, VIL=0.2Vdc, VIH=VDD–0.2Vdc.
(5) Run (operating) IDD, Wait IDD: Measured using external square wave clock source to OSC1 (fOSC=2.0MHz), all inputs 0.2Vdc
from rail; no DC loads, less than 50pF on all outputs, CL=20pF on OSC2.
(6) Stop IDD measured with OSC1=VSS.
(7) Wait IDD is affected linearly by the OSC2 capacitance.
TPG
77
05SR3.Book Page 3 Thursday, August 4, 2005 1:08 PM
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