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參數(shù)資料
| 型號(hào)： | MC68HC05B16 |
| 廠商： | Motorola, Inc. |
| 元件分類： | DC/DC變換器 |
| 英文描述： | RS-S_D(Z) Series - Econoline Regulated DC-DC Converters; Input Voltage (Vdc): 24V; Output Voltage (Vdc): 15V; Power: 2W; 2:1 and 4:1 Wide Input Voltage Ranges; 1kVDC, 2kVD & 3kVDC Isolation; UL94V-0 Package Material; Continuous Short Circuit Protection; Low Noise; No External Capacitor needed; Efficiency to 83% |
| 中文描述： | 高密度互補(bǔ)金屬氧化物半導(dǎo)體（HCMOS）微機(jī)組 |
| 文件頁(yè)數(shù)： | 50/96頁(yè) |
| 文件大?。?/td> | 3045K |
| 代理商： | MC68HC05B16 |
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Freescale
7-4
MC68HC05SR3
ANALOG TO DIGITAL CONVERTER
7
Using a port D pin as both an analog and digital input simultaneously is prohibited. When the ADC
is enabled (ADON=1) and one of channels 0 to 5 is selected, the corresponding Port D pin will
appear as a logic zero when read from the Port Data Register.
7.3
ADC Data Register (ADDR)
The ADDR stores the result of a valid ADC conversion when the COCO bits is set in ADSCR.
7.4
ADC during Low Power Modes
The ADC continues normal operation in WAIT mode. To reduce power consumption in WAIT
mode, the ADON and ADRC bits in the ADSCR should be cleared if the ADC is not used. If the
ADC is in use and the internal bus clock is above 1MHz, it is recommended that the ADRC bit be
cleared.
In STOP mode, the ADC stops operation.
Table 7-1 ADC Channel Assignments
CH2
CH1
CH0
Channel
Selected Signal
0
AD0 on PD0
0
1
AD1 on PD1
0
1
0
2
AD2 on PD2
0
1
3
AD3 on PD3
10
0
4
VRH
10
1
5
VRL
11
0
6
(VRH–VRL) ÷ 4
11
1
7
(VRH–VRL) ÷ 2
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$0F
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
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TPG
52
05SR3.Book Page 4 Thursday, August 4, 2005 1:08 PM
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