參數(shù)資料
型號: ST72F321M
廠商: 意法半導體
英文描述: 80-PIN 8-BIT MCU WITH 32 TO 60K FLASH/ROM, ADC, FIVE TIMERS, SPI, SCI, I2C INTERFACE(具有ICP,IAP,Nested Interrupt,TLI,ROP的8位MCU)
中文描述: 80引腳8位微控制器32至60,000閃存/ ROM,ADC的,5個定時器,SPI和SCI的I2C接口(具有比較方案,國際檢察官聯(lián)合會,嵌套中斷,中華語文研習所,人事登記的8位微控制器)
文件頁數(shù): 39/178頁
文件大?。?/td> 3121K
代理商: ST72F321M
ST72F321M, ST72321BM
39/178
7.7 EXTERNAL INTERRUPT CONTROL REGISTER (EICR)
Read/Write
Reset Value: 0000 0000 (00h)
Bit 7:6 =
IS1[1:0]
ei2 and ei3 sensitivity
The interrupt sensitivity, defined using the IS1[1:0]
bits, is applied to the following external interrupts:
- ei2 (port B3..0)
- ei3 (port B7..4)
These 2 bits can be written only when I1 and I0 of
the CC register are both set to 1 (level 3).
Bit 5 =
IPB
Interrupt polarity for port B
This bit is used to invert the sensitivity of the port B
[3:0] external interrupts. It can be set and cleared
by software only when I1 and I0 of the CC register
are both set to 1 (level 3).
0: No sensitivity inversion
1: Sensitivity inversion
Bit 4:3 =
IS2[1:0]
ei0 and ei1 sensitivity
The interrupt sensitivity, defined using the IS2[1:0]
bits, is applied to the following external interrupts:
- ei0 (port A3..0)
- ei1 (port F2..0)
These 2 bits can be written only when I1 and I0 of
the CC register are both set to 1 (level 3).
Bit 2 =
IPA
Interrupt polarity for port A
This bit is used to invert the sensitivity of the port A
[3:0] external interrupts. It can be set and cleared
by software only when I1 and I0 of the CC register
are both set to 1 (level 3).
0: No sensitivity inversion
1: Sensitivity inversion
Bit 1 =
TLIS
TLI sensitivity
This bit allows to toggle the TLI edge sensitivity. It
can be set and cleared by software only when
TLIE bit is cleared.
0: Falling edge
1: Rising edge
Bit 0 =
TLIE
TLI enable
This bit allows to enable or disable the TLI capabil-
ity on the dedicated pin. It is set and cleared by
software.
0: TLI disabled
1: TLI enabled
Note
: a parasitic interrupt can be generated when
clearing the TLIE bit.
7
0
IS11
IS10
IPB
IS21
IS20
IPA
TLIS
TLIE
IS11 IS10
External Interrupt Sensitivity
IPB bit =0
IPB bit =1
0
0
Falling edge &
low level
Rising edge only
Falling edge only
Rising and falling edge
Rising edge
& high level
Falling edge only
Rising edge only
0
1
1
1
0
1
IS11 IS10
External Interrupt Sensitivity
0
0
1
1
0
1
0
1
Falling edge & low level
Rising edge only
Falling edge only
Rising and falling edge
IS21 IS20
External Interrupt Sensitivity
IPA bit =0
IPA bit =1
0
0
Falling edge &
low level
Rising edge only
Falling edge only
Rising and falling edge
Rising edge
& high level
Falling edge only
Rising edge only
0
1
1
1
0
1
IS21 IS20
External Interrupt Sensitivity
0
0
1
1
0
1
0
1
Falling edge & low level
Rising edge only
Falling edge only
Rising and falling edge
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