參數(shù)資料
型號: ST72F321M
廠商: 意法半導(dǎo)體
英文描述: 80-PIN 8-BIT MCU WITH 32 TO 60K FLASH/ROM, ADC, FIVE TIMERS, SPI, SCI, I2C INTERFACE(具有ICP,IAP,Nested Interrupt,TLI,ROP的8位MCU)
中文描述: 80引腳8位微控制器32至60,000閃存/ ROM,ADC的,5個定時器,SPI和SCI的I2C接口(具有比較方案,國際檢察官聯(lián)合會,嵌套中斷,中華語文研習(xí)所,人事登記的8位微控制器)
文件頁數(shù): 169/178頁
文件大小: 3121K
代理商: ST72F321M
ST72F321M, ST72321BM
169/178
13 ST72321 DEVICE CONFIGURATION AND ORDERING INFORMATION
Each device is available for production in user pro-
grammable versions (FLASH) as well as in factory
coded versions (ROM/FASTROM).
ST72321B devices are ROM versions. ST72P321
devices are Factory Advanced Service Technique
ROM (FASTROM) versions: they are factory-pro-
grammed HDFlash devices. FLASH devices are
shipped to customers with a default content, while
ROM/FASTROM factory coded parts contain the
code supplied by the customer. This implies that
FLASH devices have to be configured by the cus-
tomer using the Option Bytes while the ROM/FAS-
TROM devices are factory-configured.
13.1 FLASH OPTION BYTES
The option bytes allow the hardware configuration
of the microcontroller to be selected. They have no
address in the memory map and can be accessed
only in programming mode (for example using a
standard ST7 programming tool). The default con-
tent of the FLASH is fixed to FFh. To program the
FLASH devices directly using ICP, FLASH devices
are shipped to customers with the internal RC
clock source. In masked ROM devices, the option
bytes are fixed in hardware by the ROM code (see
option list).
OPTION BYTE 0
OPT7=
WDG HALT
Watchdog and HALT mode
This option bit determines if a RESET is generated
when entering HALT mode while the Watchdog is
active.
0: No Reset generation when entering Halt mode
1: Reset generation when entering Halt mode
OPT6=
WDG SW
Hardware or software watchdog
This option bit selects the watchdog type.
0: Hardware (watchdog always enabled)
1: Software (watchdog to be enabled by software)
OPT5 = Reserved, must be kept at default value.
OPT4:3=
VD[1:0]
Voltage detection
These option bits enable the voltage detection
block (LVD, and AVD) with a selected threshold for
the LVD and AVD (EVD+AVD).
Caution:
If the medium or low thresholds are se-
lected, the detection may occur outside the speci-
fied operating voltage range. Below 3.8V, device
operation is not guaranteed.
STATIC OPTION BYTE 0
7
0
STATIC OPTION BYTE 1
7
0
WDG
R
VD
R
P
F
P
R
OSCTYPE
OSCRANGE
P
H
S
1
0
1
0
2
1
0
Default
1
1
1
0
0
1
1
1
1
1
1
0
1
1
1
1
Selected Low Voltage Detector
VD1
VD0
LVD and AVD Off
1
1
0
0
1
0
1
0
Lowest Threshold: (V
DD
~3V)
Med. Threshold (V
DD
~3.5V)
Highest Threshold (V
DD
~4V)
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