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| 型號(hào)： | MCIMX507CVM8B |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA400 |
| 封裝： | 17 X 17 MM, 0.5 MM PITCH, ROHS COMPLIANT, PLASTIC, MABGA-400 |
| 文件頁(yè)數(shù)： | 29/120頁(yè) |
| 文件大?。?/td> | 1980K |
| 代理商： | MCIMX507CVM8B |
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i.MX50 Applications Processors for Consumer Products, Rev. 0
16
Freescale Semiconductor
Modules List
3.1
Special Signal Considerations
Table 5 lists special signal considerations for the i.MX50. The signal names are listed in alphabetical
order. The package contact assignments are found in Section 5, “Package Information and Contact
Assignments.” The signal descriptions are defined in the MCIMX50 Applications Processor Reference
Manual (MCIMX50RM).
Table 5. Special Signal Considerations
Signal Name
Remarks
BOOT_MODE0,
BOOT_MODE1
These two input pins are sampled out of reset and set the boot mode. For Internal boot, they should
be set to 00. For Internal Fuse Only boot, they should be set to 10. For USB downloader, they
should be set to 11. The BOOTMODE pins are in the NVCC_RESET domain and include an
internal 100K pull-up resistor at start-up.
BOOT_CONFIG1[7:0],
BOOT_CONFIG2[7:0],
BOOT_CONFIG3[7:0]
These 24 pins are the GPIO boot override pins and may be driven at power up to select the boot
mode. They are sampled 4 x CKIL clock cycles after POR is de-asserted. Consult the “System
Boot” chapter of the Reference Manual for more details.
Note that these are not dedicated pins: the BOOT_CONFIG pins appear over 24 pins of the EIM
interface.
BT_LPB_FREQ[1:0]
If the LOW_BATT_GPIO (UART4_TXD) is asserted at power up, the BT_LPB_FREQ[1:0] pins will
be sampled to determine the ARM core frequency. Consult the “System Boot” chapter of the
Reference Manual for more details.
Note that these are not dedicated pins: BT_LPB_FREQ0 appears on SSI_TXFS and
BT_LPB_FREQ1 appears on SSI_TXC.
CHRG_DET_B
This is the USB Charger Detect pin. It is an open drain output pin that expects a 100 K pull-up. This
pin is asserted low when a USB charger is detected on the OTG PHY DP and DM. This detection
occurs with the application of VBUS. This pin is a raw sensor output and care must be taken to
follow the system timings outlined in the USB charger specification Rev 1.1. This pin can be
controlled by software control as well. If not used, this pin should be tied to ground or left floating.
CKIH
This is an input to the CAMPs (Clock Amplifiers), which include on-chip AC-coupling precluding
the need for external coupling capacitors. The CAMPs are enabled by default, but the main clocks
feeding the on-chip clock tree are sourced from XTAL/EXTAL by default. Optionally, the use of a
low jitter external oscillators to feed CKIH (while not required) can be an advantage if low jitter or
special frequency clock sources are required by modules sourced by CKIH. See CCM chapter in
the MCIMX50 Applications Processor Reference Manual (MCIMX50RM) for details on the
respective clock trees.
After initialization, the CAMPs may be disabled if not used by programming the CCR CAMPx_EN
field. If disabled, the on-chip CAMP output is low and the input is irrelevant. CKIH is on the
NVCC_JTAG power domain, so the input clock amplitude should not exceed NVCC_JTAG.
If unused, the user should tie CKIH to GND for best practice.
CKIL/ECKIL
The user must tie a fundamental mode 32.768 K crystal across ECKIL and CKIL. The target ESR
should be 50 K or less. The bias resistor for the amplifier is integrated and approximately 14 M
Ω.
The target load capacitance for the crystal is approximately 10 pF. The load capacitors on the
board should be slightly less than double this value after taking parasitics into account. While
driving in an external 32 KHz signal into ECKIL, CKIL should be left floating so that it biases. A
differential amplifier senses these two pins to propagate the clock inside the i.MX508. Care must
be taken to minimize external leakages on ECKIL and CKIL. If they are significant to the 14 M
Ω
feedback or 1
μA, then loss of oscillation margin or cessation of oscillation may result.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MCIMX508CVK8A | 制造商:Freescale Semiconductor 功能描述:CODEX 13MM W/2025D - Bulk |
| MCIMX508CVK8B | 功能描述:處理器 - 專門(mén)應(yīng)用 Codex 1.1 13mm RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
| MCIMX508CVK8BR2 | 功能描述:處理器 - 專門(mén)應(yīng)用 Codex 1.1 13mm RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
| MCIMX508CVM8B | 功能描述:處理器 - 專門(mén)應(yīng)用 Codex Rev 1.1 RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
| MCIMX508CVM8BR2 | 功能描述:處理器 - 專門(mén)應(yīng)用 Codex Rev 1.1 RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
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