參數資料
型號: MC68HC05P3
廠商: Motorola, Inc.
元件分類: DC/DC變換器
英文描述: RS3-S_D(Z) Series - Econoline Regulated DC-DC Converters; Input Voltage (Vdc): 12V; Output Voltage (Vdc): 05V; Power: 3W; 2:1 and 3:1 Wide Input Voltage Ranges; 1kVDC, 2kVDC & 3kVDC Isolation; UL94V-0 Package Material; Continuous Short Circuit Protection; Low Ripple and Noise; Remote On/Off Control; Efficiency to 83%
中文描述: 微機單位的16位可編程定時器
文件頁數: 66/96頁
文件大?。?/td> 3045K
代理商: MC68HC05P3
MC68HC05SR3
Freescale
9-1
LOW POWER MODES
9
LOW POWER MODES
The MC68HC05SR3 has three low-power operating modes. The WAIT and STOP instructions
provide two modes that reduce the power required for the MCU by stopping various internal clocks
and/or the on-chip oscillator. The flow of the STOP and WAIT modes is shown in Figure 9-1. The
third low-power operating mode is the SLOW mode.
9.1
STOP Mode
Execution of the STOP instruction places the MCU in its lowest power consumption mode. In the
STOP mode the internal oscillator is turned off, halting all internal processing.
When the CPU enters STOP mode the I-bit in the Condition Code Register is cleared
automatically, so that any hardware interrupts (IRQ, IRQ2 and KBI) can “wake” the MCU. All other
registers and memory contents remain unaltered. All input/output lines remain unchanged.
The MCU can be brought out of the STOP mode only by a hardware interrupt or an externally
generated reset. When exiting the STOP mode the internal oscillator will resume after a
pre-defined number of internal processor clock cycles, due to oscillator stabilization.
9.2
WAIT Mode
The WAIT instruction places the MCU in a low-power mode, but consumes more power than the
STOP mode. In the WAIT mode the internal processor clock is halted, suspending all processor
and internal bus activities. Other Internal clocks remain active, permitting interrupts to be
generated from the Timer. The Timer may be used to generate a periodic exit from the WAIT mode
or, in conjunction with the external Timer pin, on the occurrence of external events. Execution of
the WAIT instruction automatically clears the I-bit in the Condition Code Register, so that any
hardware interrupt can “wake” the MCU. All other registers, memory, and input/output lines remain
in their previous states.
TPG
67
05SR3.Book Page 1 Thursday, August 4, 2005 1:08 PM
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