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參數(shù)資料
| 型號(hào)： | MC68306PV16 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 16.67 MHz, MICROPROCESSOR, PQFP144 |
| 封裝： | PLASTIC, TQFP-144 |
| 文件頁(yè)數(shù)： | 30/191頁(yè) |
| 文件大?。?/td> | 1311K |
| 代理商： | MC68306PV16 |
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MOTOROLA
MC68306 USER'S MANUAL
6-17
can be programmed to appear on output pin OP3 (inverted). The timer runs continuously
and cannot be stopped by the CPU. Because the timer cannot be stopped, the count
value (DUCUR/DUCLR) should not be read. When a read at the start counter command
address is performed, the timer terminates the current countdown sequence, clears its
output, reinitializes itself with the preload value, and begins a new countdown sequence.
Upon reaching $0000 (terminal count), the timer inverts its output, reinitializes itself with
the preload value, and repeats the countdown sequence. If the timer output toggled from
one to zero, the CTR/TMR_RDY bit (DUISR[3]) is also set. The timer can be programmed
to generate an interrupt request for this condition on the IRQ or TIRQ output. If the preload
value is changed by the CPU, the timer will not recognize the new value until it reaches
the next terminal count (and must reinitialize itself). This feature is very useful when
generating variable duty cycle square waves. When a read at the stop counter command
address is performed, the timer clears DUISR bit 3 but does not stop. Because in timer
mode the counter/timer runs continuously, it should be completely configured (preload
value loaded and start counter command issued) before programming the timer output to
appear on OP3.
6.3.6 Bus Operation
This section describes the operation of the bus during read, write, and interrupt
acknowledge cycles to the serial module. All serial module registers must be accessed as
bytes.
6.3.6.1 READ CYCLES. The serial module is accessed by the CPU with a variable
number of wait states, depending on the relative phase of the CPU and serial module
clocks. The maximum number of wait states for a 16.67 MHz CPU clock and 3.6864 MHz
serial module clock is six. The serial module responds to reads with byte data on D7–D0.
Reserved registers return logic zero during reads.
6.3.6.2 WRITE CYCLES. The serial module is accessed by the CPU with a variable
number of wait states, up to six. The serial module accepts write data on D7–D0. Write
cycles to read-only registers and reserved registers complete in a normal manner without
exception processing; however, the data is ignored.
6.3.6.3 INTERRUPT ACKNOWLEDGE CYCLES. The serial module is capable of
arbitrating for interrupt servicing and supplying the interrupt vector when it has
successfully won arbitration. The vector number must be provided if interrupt servicing is
necessary; thus, the interrupt vector register (DUIVR) must be initialized. If the DUIVR is
not initialized, a spurious interrupt exception will be taken if interrupts are generated.
6.4 REGISTER DESCRIPTION AND PROGRAMMING
This section contains a detailed description of each register and its specific function as
well as flowcharts of basic serial module programming.
6.4.1 Register Description
The operation of the serial module is controlled by writing control bytes into the
appropriate registers. A list of serial module registers and their associated addresses is
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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