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參數(shù)資料
| 型號(hào)： | MC68306PV16 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 16.67 MHz, MICROPROCESSOR, PQFP144 |
| 封裝： | PLASTIC, TQFP-144 |
| 文件頁(yè)數(shù)： | 112/191頁(yè) |
| 文件大?。?/td> | 1311K |
| 代理商： | MC68306PV16 |
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MOTOROLA
MC68306 USER'S MANUAL
2- 7
BGACK can be negated (pulled high), and the MC68306 will operate in a two-wire bus
arbitration system.
2.1.7 Data Bus (D15–D0)
This bi-directional, three-state bus is the general-purpose data path. It is 16 bits wide and
can transfer and accept data of either word or byte length. During an interrupt
acknowledge cycle, an external device can supply the interrupt vector number on data
lines D7–D0.
2.1.8 Data Transfer Acknowledge (
DTACK)
Assertion of this bi-directional, open-drain signal indicates the completion of the data
transfer. When the processor recognizes DTACK during a read cycle, data is latched, and
the bus cycle is terminated. When DTACK is recognized during a write cycle, the bus
cycle is terminated. The MC68306 generates DTACK for all internal cycles, DRAM cycles,
and autovector IACK cycles, and can be programmed to generate DTACK for any chip
select cycle. (Refer to 3.7 Asynchronous Operation and 3.8 Synchronous Operation.)
2.1.9 DRAM Multiplexed Address Bus (DRAMA14–DRAMA0)
These signals provide fifteen multiplexed address bits used during row address strobe.
2.1.10 Processor Function Codes (FC2–FC0)
These function code outputs indicate the mode (user or supervisor) and the address
space type currently being accessed, as shown in Table 2-8. The function code outputs
are valid whenever AS is asserted.
Table 2-8. Function Code Outputs
Function Code Output
FC2
FC1
FC0
Address Space Type
Low
(Undefined, Reserved)
Low
High
User Data
Low
High
Low
User Program
Low
High
(Undefined, Reserved)
High
Low
(Undefined, Reserved)
High
Low
High
Supervisor Data
High
Low
Supervisor Program
High
CPU Space
2.1.11 Halt (
HALT)
External assertion of this bi-directional signal causes the processor to stop bus activity at
the completion of the bus cycle for which the input met set-up time requirements (i.e.,
current or next cycle). This operation places all control signals in the inactive state. For
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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