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參數(shù)資料
| 型號： | MC33689DWB |
| 廠商： | Motorola, Inc. |
| 英文描述： | Single Output LDO, 400mA, Fixed(2.85V), Low Noise, Fast Transient Response 8-MSOP -40 to 85 |
| 中文描述： | 系統(tǒng)基礎芯片收發(fā)器和LIN |
| 文件頁數(shù)： | 17/18頁 |
| 文件大?。?/td> | 229K |
| 代理商： | MC33689DWB |
MC33689
8
MC33689
Delay between CSB wake up (CSB low
to high) and first accepted SPI command
Tw-spi
90
N/A
us
SBC in stop mode
Delay between INT pulse and 1st SPI
command accepted
Ts-1stspi
30
N/A
us
In stop mode after wake up
The minimum time between two rising
edges on the CSB
T2csb
15
us
note 1: when IN input is set to high, delay starts at falling edge of clock cycle #8 of the SPI command and start of device activation/deactivation.
30mA load on HS switches. Excluding rise or fall time due to external load.
note 2: when IN used to control HS switches, delays measured betxween IN and HS1 or HS2 on /off. 30mA load on HS switches. Excluding
rise or fall time due to external load.
Rx: LIN physical layer output
Low Level Voltage Output
Vol
0
0.9
V
I in
≤ +1.5mA
High Level Voltage Output
Voh
3.75
5.25
V
I out
≤ 250uA
Tx: LIN physical layer input
Low Level Voltage Input
Vil
1.5
V
High Level Voltage Input
Vih
3.5
V
Input Threshold Hysteresis
Vinhyst
50
550
800
mV
Pull-up Current Source
Is
-100
-20
uA
1V <V(Tx) < 3.5V
LIN: physical layer bus (Voltage Expressed versus Vsup Voltage)
Low Level Dominant Voltage
Vlin-low
1.4
V
external bus pull 500 Ohms
High Level Voltage (Tx high, Iout = 1uA)
Vlin-high
Vsup-1
V
Recessive state
Pull up Resistor to Vsup
Rpu
20
30
47
kohms
In normal mode. In sleep and
stop mode if not turned off by
SPI
Pull up current source
Ipu
1.3
uA
In sleep and stop mode with
30k disconnected
Over current shutdown threshold
Iov-cur
50
75
150
mA
Over current shutdown delay
Iov-delay
10
us
Guaranteed by design
Leakage Current to GND
Ibus-pas-
rec
0
3
20
uA
Recessive state, Vsup 8V to
18V, Vlin 8V to 18V
Gnd disconnected, Vgnd = Vsup, VLin at
-18V
Ibus no
gnd
-1
1
mA
Leakage Current to GND, Vsup Discon-
nected, VLin at +18V
Ibus
1
10
uA
Vsup disconnected
Vlin at +18V
Lin Receiver Vil (Tx high, Rx low)
Lin-vil
0
0.4VSUP
Lin Receiver Vih (Tx high, Rx high)
Lin-vih
0.6 VSUP
VSUP
LIN Receiver Threshold center
Lin-thres
0.475
0.5
0.525
Vsup
(Lin-vih - Lin-vil) / 2
LIN Receiver Input Hysteresis
LIN hyst
0.175
Vsup
Lin-vih - Lin-vil
LIN wake up threshold
LIN wu
0.5
Vsup
LIN physical layer: bus driver timing characteristics for normal slew rate (note 1)
Dominant propagation delay Tx to LIN
tdom min
50
us
Measurement threshold
58.1% Vsup
Dominant propagation delay Tx to LIN
tdom max
50
us
Measurement threshold
28.4% Vsup
Recessive propagation delay Tx to LIN
trec min
50
us
Measurement threshold
42.2% Vsup
Recessive propagation delay Tx to LIN
trec max
50
us
Measurement threshold
74.4% Vsup
Prop delay symmetry: tdom min - trec
max
dt1
-10.44
-
us
(Vs1 and Vs2 from 5.5V to 18V and Tamb from -40°C to 125°C unless otherwise noted)
Description
Symbol
Characteristics
Unit
Conditions
Min
Typ
Max
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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