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參數(shù)資料
| 型號(hào)： | MC33689DWB |
| 廠商： | Motorola, Inc. |
| 英文描述： | Single Output LDO, 400mA, Fixed(2.85V), Low Noise, Fast Transient Response 8-MSOP -40 to 85 |
| 中文描述： | 系統(tǒng)基礎(chǔ)芯片收發(fā)器和LIN |
| 文件頁(yè)數(shù)： | 16/18頁(yè) |
| 文件大?。?/td> | 229K |
| 代理商： | MC33689DWB |
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MC33689
7
MC33689
note 1: when over temperature occurs, switch is turned off and latched off. Flag is set in SPI.
HS3: High side output pin
Rdson at Tj=25°C, and Iout -50mA
Ron25
7
Ohms
Vsup>9V
Rdson at Ta=125°C, and Iout -50mA
Ron125
10
Ohms
Vsup>9V
Rdson at Ta=125°C, and Iout -30mA
Ron3
14
Ohms
5.5<Vsup<9V
Output current limitation
Ilim
60
100
200
mA
Over temperature Shutdown
Ovt
155
190
°C
note 1
Leakage current
Ileak
10
uA
note 1: when over temperature occurs, switch is turned off and latched off. Flag is set in SPI
SENSE CURRENT AMPLIFIER SECTION:
Rail to rail input voltage
Vimc
-0.1
Vcc+0.1
V
Output voltage range
Vout1
0.1
Vcc-0.1
V
Output current +- 1mA
Output voltage range
Vout2
0.3
Vcc-0.3
V
Output current +-5 mA
Input bias current
Ib
250
nA
Input offset current
Io
-100
100
nA
Input offset voltage
Vio
-15
15
mV
Supply voltage rejection ratio
SVR
60
dB
Guaranteed by design
Common mode rejection ratio
CMR
70
dB
Guaranteed by design
Gain bandwidth
GBP
1
Mhz
Guaranteed by design
Slew rate
SR
0.5
V/us
Phase margin
PHMO
40
°
For gain=1,load 100pF//
5kohms. Guaranteed by design
Open loop gain
OLG
85
dB
Guaranteed by design
L1, L2 inputs
Negative Switching Threshold
Vthn
2
2.5
2.7
2.5
3
3.2
3
3.5
3.7
V
5.5V<Vsup<6V
6V<Vsup<18V
18V<Vsup<27
Positive Switching Threshold
Vthp
2.7
3
3.5
3.3
4
4.2
3.8
4.5
4.7
V
5.5V<Vsup<6V
6V<Vsup<18V
18V<Vsup<27
Hysteresis
Vhyst
0.5
1.3
V
5.5V<Vsup<27
Input current
Iin
-10
10
uA
-0.2V < Vin < 40V
Wake up Filter Time
Twuf
8
20
38
us
Guaranteed by design
STATE MACHINE TIMING
Delay between CSB low to high transition
(at end of SPI stop command) and Stop
mode activation (Guaranteed by design)
Tstop-m
Tstop-nw
Tstop-M
1.4
6
12
5
30
50
us
Minimum Watchdog period
No watchdog selected
Maximum watchdog period
Interrupt low level duration
Tint
7
10
13
us
Internal oscillator frequency accuracy
Osc-f1
-35
35
%
All modes, for info only
Normal request mode time out
NRtout
97
150
205
ms
Normal request mode
Delay between SPI command and HS1,
HS2 or HS3 turn on (note 1, 2)
Ts-HSon
20
us
Normal mode
Vsup>9V, Vhs >= 0.2 Vs1
Delay between SPI command and HS1,
HS2 or HS3 turn off (note 1, 2)
Ts-HSoff
20
us
Normal mode
Vsup>9V, Vhs <= 0.8 Vs1
Delay between Normal Request and Nor-
mal mode, after W/D trigger command
Ts-NR2N
6
35
30
us
Normal request mode, Guar-
anteed by design
Delay between CSB wake up (CSB low
to high) and SBC normal request mode
(Vdd1 on & reset high)
Tw-csb
15
40
80
us
SBC in stop mode
(Vs1 and Vs2 from 5.5V to 18V and Tamb from -40°C to 125°C unless otherwise noted)
Description
Symbol
Characteristics
Unit
Conditions
Min
Typ
Max
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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