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| 型號： | MC16V1CPU20B1 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, 20.97 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數(shù)： | 55/128頁 |
| 文件大?。?/td> | 571K |
| 代理商： | MC16V1CPU20B1 |
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MOTOROLA
MC68HC16V1
32
MC68HC16V1TS/D
3.4.5 Software Watchdog
The software watchdog (SWDOG) monitors system software and protects against possible errors oc-
curring in the system which might allow software to become trapped in loops with no controlled exit.
User code must regularly write the servicing sequence to the SWSR to prevent the software watchdog
from timing out. If this real-time servicing action does not take place, the software watchdog issues ei-
ther a reset or an interrupt.
Software watchdog features include:
The ability to select between an interrupt or a reset at the end of a time-out period.
The input clock to the software downcounter (SWDC) may be the system clock divided by two (fsys
÷ 2), the clock synthesizer reference frequency divided by 2 (f
ref ÷ 2), or the output of the system
protection prescaler. Time-out periods range from 61
s to 4096 seconds (with a 32.768 kHz crys-
tal frequency) or from 95.4 ns to 6.4 seconds (with a 20.97 MHz external clock).
SWDC can be chained together with the real-time downcounter to create a 32-bit downcounter for
extended time-out periods.
SWDC is readable at any time.
The software watchdog service register (SWSR) is controlled by SWE in SYPCR. Once enabled, the
watchdog requires that a service sequence be written to SWSR on a periodic basis. If servicing does
not take place, the watchdog times out and issues a reset or generates an interrupt. This register can
be written at any time, but returns zeros when read.
Each time the service sequence is written, the software watchdog timer restarts. The sequence to re-
start consists of the following steps:
Write $55 to SWSR
Write $AA to SWSR
Both writes must occur before time-out in the order listed, but any number of instructions, up to the end
of the time-out period, can be executed between the two writes.
When the proper service sequence occurs, the software watchdog downcounter reloads the value of
the software watchdog period register and the process begins again.
If the time-out period is reached before a service action, the software watchdog causes a reset, or an
interrupt, depending on the state of the IRSEL bit. If the software watchdog causes reset, the SW flag
in the reset status register (RSR) is also set.
The software watchdog and the real-time clock share a 10-bit synchronous counter, the prescaler
(SLIMPRE). Different prescaler taps can be applied simultaneously to either the software watchdog or
real-time clock downcounter. A read of unused bits always returns zero. Writes have no effect.
SWSR — Software Watchdog Service Register
$YFFA55
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
UNUSED
SWSR
RESET:
0
SLIMPRE — System Protection Prescaler
$YFFA56
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
UNUSED
POWER-ON RESET ONLY:
0
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