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| 型號(hào)： | MC16V1CPU20B1 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, 20.97 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁(yè)數(shù)： | 125/128頁(yè) |
| 文件大?。?/td> | 571K |
| 代理商： | MC16V1CPU20B1 |
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MOTOROLA
MC68HC16V1
96
MC68HC16V1TS/D
FRZ1 — FREEZE Assertion Response
0 = Ignore the FREEZE signal on the IMB
1 = Halt the QSPI (on a transfer boundary)
FRZ1 determines what action is taken by the QSPI when the FREEZE signal of the IMB is asserted.
FREEZE is asserted whenever the CPU enters the background mode.
FRZ0 — Not Implemented
Bits [12:8] — Not Implemented
SUPV — Supervisor/Unrestricted Data Space
This bit has no effect because the CPU16 always operates in the supervisor mode.
IARB[3:0] — Interrupt Arbitration Identification Number
The IARB field is used to arbitrate between simultaneous interrupt requests of the same priority. Each
module that can generate interrupt requests must be assigned a unique, non-zero IARB field value.
QTEST — QSM Test Register
$YFFC02
QTEST is used during factory testing of the QSM.
QILR determines the priority level of interrupts requested by the QSM.
ILQSPI[2:0] — Interrupt Level for QSPI
ILQSPI determines the priority of QSPI interrupts. This field must be given a value between $0 (inter-
rupts disabled) to $7 (highest priority).
ILSCI[2:0] — Interrupt Level of SCI
ILSCI determines the priority of SCI interrupts. This field must be given a value between $0 (interrupts
disabled) to $7 (highest priority).
If ILQSPI and ILSCI are the same nonzero value, and both submodules simultaneously request inter-
rupt service, QSPI has priority.
At reset, QIVR is initialized to $0F, which corresponds to the uninitialized interrupt vector in the excep-
tion table. This vector is selected until QIVR is written. A user-defined vector ($40–$FF) should be writ-
ten to QIVR during QSM initialization.
After initialization, QIVR determines which two vectors in the exception vector table are to be used for
QSM interrupts. The QSPI and SCI submodules have separate interrupt vectors adjacent to each other.
Both submodules use the same interrupt vector with the least significant bit (LSB) determined by the
submodule causing the interrupt.
QILR — QSM Interrupt Levels Register
$YFFC04
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ILQSPI[2:0]
ILSCI[2:0]
QIVR
RESET:
0
QIVR — QSM Interrupt Vector Register
$YFFC05
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
QILR
INTV[7:0]
RESET:
0
1
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