
TMS370Cx9x
8-BIT MICROCONTROLLER
SPNS036B – JANUARY 1996 – REVISED FEBRUARY 1997
24
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
timer 1 module (continued)
Hard watchdog configuration for mask-ROM device only (see Figure 9)
–
Eight different WD overflow rates ranging from 26.2 ms to 3.35 s at 5-MHz SYSCLK
–
A WD reset key (WDRST) register is used to clear the watchdog counter (WDCNTR) when a correct
value is written.
–
Generates a system reset if an incorrect value is written to the watchdog reset key or if the counter
overflows.
–
Automatic activation of the WD timer upon power-up reset
–
INT1 is enabled as nonmaskable interrupt during low-power modes
–
A WD overflow flag (WD OVRFL INT FLAG) bit that indicates whether the WD timer initiated a system
reset.
16-Bit
Watchdog Counter
Reset
Prescaler
Clock
Watchdog Reset Key
WD OVRFL
TAP SEL
System Reset
T1CTL1.7
WDRST.7-0
WDCNTR.15-0
T1CTL2.5
WD OVRFL
INT FLAG
Figure 9. Hard Watchdog