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    參數(shù)資料
    型號: TMS370CX7XJN
    廠商: Texas Instruments, Inc.
    元件分類: 8位微控制器
    英文描述: 8-BIT MICROCONTROLLER
    中文描述: 8位微控制器
    文件頁數(shù): 44/54頁
    文件大小: 785K
    代理商: TMS370CX7XJN
    TMS370Cx9x
    8-BIT MICROCONTROLLER
    SPNS036B – JANUARY 1996 – REVISED FEBRUARY 1997
    44
    POST OFFICE BOX 1443
    HOUSTON, TEXAS 77251–1443
    external clocking requirements for clock divided by 4
    (see Figure 19)
    NO.
    PARAMETER
    MIN
    MAX
    UNIT
    1
    tw(Cl)
    tr(Cl)
    tf(CI)
    td(CIH-SCL)
    CLKIN
    Pulse duration, XTAL2/CLKIN (see Note 9)
    20
    ns
    2
    Rise time, XTAL2/CLKIN
    30
    ns
    3
    Fall time, XTAL2/CLKIN
    30
    ns
    4
    Delay time, XTAL2/CLKIN rise to SYSCLK fall
    100
    ns
    Crystal operating frequency
    System clock
    2
    20
    MHz
    SYSCLK
    0.5
    5
    MHz
    For VIL and VIH, refer to recommended operating conditions.
    SYSCLK = CLKIN/4
    NOTE 9: This pulse can be either a high pulse, which extends from the earliest valid high to the final valid high in an XTAL2/CLKIN cycle or a
    low pulse, which extends from the earliest valid low to the final valid low in an XTAL2/CLKIN cycle.
    XTAL2/CLKIN
    3
    2
    1
    4
    SYSCLK
    Figure 19. External Clock Timing for Divide-by-4
    external clocking requirements for clock divided by 1 (PLL)
    (see Figure 20)
    NO.
    1
    PARAMETER
    MIN
    20
    MAX
    UNIT
    ns
    tw(Cl)
    tr(Cl)
    tf(CI)
    td(CIH-SCH)
    CLKIN
    Pulse duration, XTAL2/CLKIN (see Note 9)
    2
    Rise time, XTAL2/CLKIN
    30
    ns
    3
    Fall time, XTAL2/CLKIN
    30
    ns
    4
    Delay time, XTAL2/CLKIN rise to SYSCLK rise
    100
    ns
    Crystal operating frequency
    System clock§
    2
    5
    MHz
    SYSCLK
    2
    5
    MHz
    For VIL and VIH, refer to recommended operating conditions.
    §SYSCLK = CLKIN/1
    NOTE 9: This pulse can be either a high pulse, which extends from the earliest valid high to the final valid high in an XTAL2/CLKIN cycle or a
    low pulse, which extends from the earliest valid low to the final valid low in an XTAL2/CLKIN cycle.
    XTAL2/CLKIN
    3
    2
    1
    4
    SYSCLK
    Figure 20. External Clock Timing for Divide-by-1
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