參數(shù)資料
型號： ST72C171K2
廠商： 意法半導體
英文描述： 8-BIT MCU WITH 8K FLASH. ADC. WDG. SPI. SCI. TIMERS SPGAS (SOFTWARE PROGRAMMABLE GAIN AMPLIFIERS). OP-AMP
中文描述： 8位8K閃存微控制器。 ADC的。水分散粒劑。的SPI。脊髓損傷。定時器SPGAS（軟件可編程增益放大器）。運放
文件頁數(shù)： 17/152頁
文件大?。?/td> 1384K
代理商： ST72C171K2
ST72C171
17/152
4.2.1 Reset Sequence Manager (RSM)
The RSM block of the CROSS Module includes
three RESET sources as shown in
Figure 10
:
I
EXTERNAL RESET SOURCE pulse
I
Internal LVD RESET (Low Voltage Detection)
I
Internal WATCHDOG RESET
These sources act on the RESET PIN and it is al-
ways kept low during the READ OPTION RESET
phase.
The RESET service routine vector is fixed at the
FFFEh-FFFFh addresses in the ST7 memory
map.
Figure 10. Reset Block Diagram
The basic RESET sequence consists of 4 phases
as shown in
Figure 11
:
I
OPTION BYTE reading to configure the device
I
Delay depending on the RESET source
I
4096 cpu clock cycle delay
I
RESET vector fetch
The duration of the OPTION BYTE reading phase
(t
ROB
) is defined in the Electrical Characteristics
section. This first phase is initiated by an external
RESET pin pulse detection, a Watchdog RESET
detection, or when V
DD
rises up to V
LVDopt
.
The 4096 cpu clock cycle delay allows the oscilla-
tor to stabilise and to ensure that recovery has tak-
en place from the Reset state.
The RESET vector fetch phase duration is 2 clock
cycles.
Figure 11. RESET Sequence Phases
f
CPU
C
RESET
R
ON
V
DD
WATCHDOG RESET
READ OPTION RESET
LVD RESET
INTERNAL
RESET
RESET
READ
OPTION BYTE
INTERNAL RESET
4096 CLOCK CYCLES
FETCH
VECTOR
DELAY
t
ROB
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ST72C215G2M5 制造商:STMicroelectronics 功能描述:MCU 8BIT ST7 CISC 8KB FLASH 3.3V/5V 28SOIC - Rail/Tube
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