參數(shù)資料
型號： ST72C171
廠商： 意法半導(dǎo)體
英文描述： 8-BIT MCU with 8K FLASH, ADC, WDG, SPI, SCI, TIMERS SPGAs Software Programmable Gain Amplifiers, OP-AMP
中文描述： 8位8K閃存，ADC的，水分散粒劑，SPI和脊髓損傷，定時器SPGAs軟件可編程增益放大器，運算放大器控制器
文件頁數(shù)： 23/152頁
文件大?。?/td> 1384K
代理商： ST72C171
ST72C171
23/152
4.4 CLOCK, RESET AND SUPPLY REGISTER DESCRIPTION
CLOCK RESET AND SUPPLY REGISTER
(CRSR)
Read/Write
Reset Value: 000x 000x (00h)
Bit 7:5 = Reserved.
Bit 4 =
LVDRF
LVD Reset Flag
This bit indicates when set that the last Reset was
generated by the LVD block. It is set by hardware
(LVD reset) and cleared by software (writing zero)
or a Watchdog Reset. See WDGRF flag descrip-
tion for more details.
Bit 3 = Reserved.
Bit 2 =
CSSIE
CSS Interrupt Enable
This bit allows to enable the interrupt when a dis-
trurbance is detected by the Clock Security Sys-
tem (CSSD bit set). It is set and cleared by soft-
ware.
0: Clock Filter interrupt disable
1: Clock Filter interrupt enable
Bit 1 =
CSSD
CSS Safe Osc. Detection
This bit indicates that the safe oscillator of the CSS
block has been selected. It is set by hardware and
cleared by reading the CRSR register when the
original oscillator recovers.
0: Safe oscillator is not active
1: Safe oscillator has been activated
Bit 0 =
WDGRF
WatchDog Reset Flag
This bit indicates when set that the last Reset was
generated by the Watchdog peripheral. It is set by
hardware (watchdog reset) and cleared by soft-
ware (writing zero) or an LVD Reset.
Combined with the LVDRF flag information, the
flag description is given by the following table.
Table 3. Supply, Reset and Clock Register Map and Reset Values
7
0
-
-
-
LVD
RF
-
CSS
IE
CSS
D
WDG
RF
RESET Sources
External RESET pin
Watchdog
LVD
LVDRF
0
0
1
WDGRF
0
1
X
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
0020h
MISCR
Reset Value
PEI3
0
PEI2
0
MCO
0
PEI1
0
PEI0
0
CP1
0
CP0
0
SMS
0
0025h
CRSR
Reset Value
-
0
-
0
-
0
LVDRF
x
-
0
CSSIE
0
CSSD
0
WDGRF
x
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