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    參數(shù)資料
    型號: PIC16LF72-I/SP
    廠商: Microchip Technology
    文件頁數(shù): 110/136頁
    文件大?。?/td> 0K
    描述: IC PIC MCU FLASH 2KX14 28DIP
    產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
    8-bit PIC® Microcontroller Portfolio
    標(biāo)準(zhǔn)包裝: 15
    系列: PIC® 16F
    核心處理器: PIC
    芯體尺寸: 8-位
    速度: 20MHz
    連通性: I²C,SPI
    外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
    輸入/輸出數(shù): 22
    程序存儲器容量: 3.5KB(2K x 14)
    程序存儲器類型: 閃存
    RAM 容量: 128 x 8
    電壓 - 電源 (Vcc/Vdd): 2 V ~ 5.5 V
    數(shù)據(jù)轉(zhuǎn)換器: A/D 5x8b
    振蕩器型: 外部
    工作溫度: -40°C ~ 85°C
    封裝/外殼: 28-DIP(0.300",7.62mm)
    包裝: 管件
    產(chǎn)品目錄頁面: 639 (CN2011-ZH PDF)
    75
    2535J–AVR–08/10
    ATtiny13
    11.9.7
    TIFR0 – Timer/Counter 0 Interrupt Flag Register
    Bits 7:4, 0 – Res: Reserved Bits
    These bits are reserved bits in the ATtiny13 and will always read as zero.
    Bit 3 – OCF0B: Output Compare Flag 0 B
    The OCF0B bit is set when a Compare Match occurs between the Timer/Counter and the data in
    OCR0B – Output Compare Register0 B. OCF0B is cleared by hardware when executing the cor-
    responding interrupt handling vector. Alternatively, OCF0B is cleared by writing a logic one to
    the flag. When the I-bit in SREG, OCIE0B (Timer/Counter Compare B Match Interrupt Enable),
    and OCF0B are set, the Timer/Counter Compare Match Interrupt is executed.
    Bit 2 – OCF0A: Output Compare Flag 0 A
    The OCF0A bit is set when a Compare Match occurs between the Timer/Counter0 and the data
    in OCR0A – Output Compare Register0. OCF0A is cleared by hardware when executing the cor-
    responding interrupt handling vector. Alternatively, OCF0A is cleared by writing a logic one to
    the flag. When the I-bit in SREG, OCIE0A (Timer/Counter0 Compare Match Interrupt Enable),
    and OCF0A are set, the Timer/Counter0 Compare Match Interrupt is executed.
    Bit 1 – TOV0: Timer/Counter0 Overflow Flag
    The bit TOV0 is set when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware
    when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by
    writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt
    Enable), and TOV0 are set, the Timer/Counter0 Overflow interrupt is executed.
    The setting of this flag is dependent of the WGM02:0 bit setting. Refer to Table 11-8, “Waveform
    Bit
    7
    65432
    10
    –––
    OCF0B
    OCF0A
    TOV0
    –TIFR0
    Read/Write
    R
    R/W
    R
    Initial Value
    0
    00000
    00
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