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  • 參數(shù)資料
    型號(hào): PIC16F76-I/SS
    廠商: Microchip Technology
    文件頁數(shù): 76/104頁
    文件大小: 0K
    描述: IC MCU FLASH 8KX14 A/D 28SSOP
    產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
    8-bit PIC® Microcontroller Portfolio
    標(biāo)準(zhǔn)包裝: 47
    系列: PIC® 16F
    核心處理器: PIC
    芯體尺寸: 8-位
    速度: 20MHz
    連通性: I²C,SPI,UART/USART
    外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
    輸入/輸出數(shù): 22
    程序存儲(chǔ)器容量: 14KB(8K x 14)
    程序存儲(chǔ)器類型: 閃存
    RAM 容量: 368 x 8
    電壓 - 電源 (Vcc/Vdd): 4 V ~ 5.5 V
    數(shù)據(jù)轉(zhuǎn)換器: A/D 5x8b
    振蕩器型: 外部
    工作溫度: -40°C ~ 85°C
    封裝/外殼: 28-SSOP(0.209",5.30mm 寬)
    包裝: 管件
    產(chǎn)品目錄頁面: 641 (CN2011-ZH PDF)
    配用: AC164307-ND - MODULE SKT FOR PM3 28SSOP
    Micrel, Inc.
    KSZ8851-16MLLJ
    March 2010
    65
    M9999-030210-1.0
    Interrupt Status Register (0x92 – 0x93): ISR (Continued)
    Bit
    Default Value
    R/W
    Description
    5
    0x0
    RO
    RXWFDIS Receive Wakeup Frame Detect Interrupt Status
    When this bit is set, it indicates that Receive wakeup frame detect status has occurred.
    Write “1000” to PMECR[5:2] to clear this bit
    4
    0x0
    RO
    RXMPDIS Receive Magic Packet Detect Interrupt Status
    When this bit is set, it indicates that Receive magic packet detect status has occurred.
    Write “0100” to PMECR[5:2] to clear this bit.
    3
    0x0
    RO
    LDIS Linkup Detect Interrupt Status
    When this bit is set, it indicates that wake-up from linkup detect status has occurred. Write
    “0010” to PMECR[5:2] to clear this bit.
    2
    0x0
    RO
    EDIS Energy Detect Interrupt Status
    When this bit is set and bit 2=1, bit 0=0 in IER register, it indicates that wake-up from
    energy detect status has occurred. When this bit is set and bit 2, 0=1 in IER register, it
    indicates that wake-up from delay energy detect status has occurred.
    Write “0001” to PMECR[5:2] to clear this bit.
    1
    0x0
    RO
    Reserved.
    0
    0x0
    RO
    Reserved
    0x94 – 0x9B: Reserved
    RX Frame Count & Threshold Register (0x9C – 0x9D): RXFCTR
    This register indicates the current total amount of received frame count in RXQ frame buffer and also is used to program
    the received frame count threshold.
    Bit
    Default Value
    R/W
    Description
    15-8
    0x00
    RO
    RXFC RX Frame Count
    To indicate the total received frames in RXQ frame buffer when receive interrupt (bit13=1 in
    ISR) occurred and write “1” to clear this bit 13 in ISR. The host CPU can start to read the
    updated receive frame header information in RXFHSR/RXFHBCR registers after read this
    RX frame count register.
    7-0
    0x00
    RW
    RXFCT Receive Frame Count Threshold
    To program received frame count threshold value.
    When bit 5 set to 1 in RXQCR register, the KSZ8851-16MLLJ will set RX interrupt (bit 13 in
    ISR) when the number of received frames in RXQ buffer exceeds the threshold set in this
    register.
    TX Next Total Frames Size Register (0x9E – 0x9F): TXNTFSR
    This register is used by the host CPU to program the total amount of TXQ buffer space requested for the next transmit.
    Bit
    Default Value
    R/W
    Description
    15-0
    0x0000
    RW
    TXNTFS TX Next Total Frames Size
    The host CPU is used to program the total amount of TXQ buffer space which is required
    for next total transmit frames size in double-word count.
    When bit 1 (TXQ memory available monitor) is set to 1 in TXQCR register, the KSZ8851-
    16MLLJ will generate interrupt (bit 6 in ISR register) to CPU when TXQ memory is
    available based upon the total amount of TXQ space requested by CPU at this register.
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