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參數(shù)資料
| 型號： | PC312XDP512F0VAAR |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | Covers, S12XD, S12XB & S12XA Families |
| 中文描述： | 封面，S12XD，S12XB |
| 文件頁數(shù)： | 117/1350頁 |
| 文件大小： | 3951K |
| 代理商： | PC312XDP512F0VAAR |
Chapter 2 Clocks and Reset Generator (S12CRGV6)
MC9S12XDP512 Data Sheet, Rev. 2.17
Freescale Semiconductor
117
2.6.2
PLL Lock Interrupt
The CRG generates a PLL Lock interrupt when the LOCK condition of the PLL has changed, either from
a locked state to an unlocked state or vice versa. Lock interrupts are locally disabled by setting the
LOCKIE bit to 0. The PLL Lock interrupt flag (LOCKIF) is set to1 when the LOCK condition has
changed, and is cleared to 0 by writing a 1 to the LOCKIF bit.
2.6.3
Self Clock Mode Interrupt
TheCRGgeneratesaselfclockmodeinterruptwhentheSCMconditionofthesystemhaschanged,either
entered or exited self clock mode. SCM conditions can only change if the self clock mode enable bit
(SCME)issetto1.SCMconditionsarecausedbyafailingclockqualitycheckafterpoweronreset(POR)
orlowvoltagereset(LVR)orrecoveryfromfullstopmode(PSTP=0)orclockmonitorfailure.Fordetails
on the clock quality check refer to
Section 2.4.1.4, “Clock Quality Checker”
. If the clock monitor is
enabled (CME = 1) a loss of external clock will also cause a SCM condition (SCME = 1).
SCM interrupts are locally disabled by setting the SCMIE bit to 0. The SCM interrupt flag (SCMIF) is set
to1 when the SCM condition has changed, and is cleared to 0 by writing a 1 to the SCMIF bit.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| PC312XDP512F0VAGR | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCS12X Microcontrollers |
| PC312XDP512F0VALR | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCS12X Microcontrollers |
| PC312XDP512F0VFUR | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCS12X Microcontrollers |
| PC312XDP512F0VFVR | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCS12X Microcontrollers |
| PC312XDP512F0VPVR | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCS12X Microcontrollers |
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