
MT9072
Data Sheet
161
Zarlink Semiconductor Inc.
17.2.2 Register Address (Y00 - YFF) Summary
Tables 137 to 146 provide a summary of each of the framer registers for the MT9072.
17.2.2.1 Master Control Registers Address (Y00-Y0F, YF0-YFF) Summary
Binary Address
(A
10
-A
0
)
Hex
Address
R/W
Register
Control Bits
(B15 - B8 / B7 - B0)
yyyy 0000 0000
Y00
R/W Alarms and
Framing Control
IMA, ASEL, ARAI, TALM, TAIS, TAIS0, TAI16, TE,
TIU0, TIU1, CSYN, REFRM, AUTC, CRCM, AUTY, MFRF
yyyy 0000 0001
Y01
R/W Test, Loopback
and Error Control
#, #, L32Z, ADSEQ, DLBK, RLBK, SLBK, PLBK,
E1, E2, BVE, CRCE, FASE, NFSE, LOSE, PERR
yyyy 0000 0010
Y02
R/W Interrupts and
I/O Control
COD1, COD0, THDB3, T2OP, MFBE,Tx8KEN, SPND,
INTA,CLKE, RHDB3, RxBFE, RxDO, RxCO, CSToE,
DSToE, MFSEL
yyyy 0000 0011
Y03
R/W DL, CCS, CAS
& Other Control
#,#, #,#,#,#,#,#,
#, ELAS, ACCLR, RxTRS, TxTRS, CSIG, CNCLR, RST
yyyy 0000 0100
Y04
R/W Signaling
InterruptPeriod
#,#,#,#,#,#,#,#,#,#,#,#,#,#,#,SIP1-0
yyyy 0000 0101
Y05
R/W CAS Control and
Data
#, #, #, #, RFL, DBNCE, #, #,
TMA1, TMA2, TMA3, TMA4, X1, Y, X2, X3
yyyy 0000 0110
Y06
R/W HDLC &CCS
ST-BUS Control
# ,#,#,#,HCH4:0,HPAYSEL,#,#,#,#,TS31E, TS16E, TS15E
yyyy 0000 0111
Y07
R/W CCS to ST-BUS
Map Control
#, 31C4, 31C3, 31C2, 31C1, 31C0, 16C4, 16C3
16C2, 16C1, 16C0, 15C4, 15C3, 15C2, 15C1, 15C0
yyyy 00001000
Y08
R/W DataLink Control
Word
Sa4SS1-0,Sa5SS1-0,Sa6SS1-0,Sa7SS1-0,
Sa8SS1-0,#,#,#E4CK,DLCK
yyyy 00001001
Y09
R/W Receive Idle
Code Word
#########RID(7:0)
yyyy 00001010
Y0A
R/W Transmit Idle
CodeWord
#########TID(7:0)
yyyy 0000 1001-
yyyy 0000 1111
Y0B-Y0F
-
not used
-
yyyy 1111 0000-
yyyy 1111 0001
YF0-YF1
-
not used
yyyy 1111 0010
YF2
R/W HDLC Control 0
#,#,#,#,ADREC,RXEN,TXEN,EOP,FA,MI,CYCLE,TCRCI,
SEVEN,RXFRST,TXFRST
yyyy 1111 0011
YF3
R/W HDLC Test
Control
#,#,#,#,#,#,#,#,#,#.HRST,
RTLoop,CRCTST,FTST,ADTST,HLOOP
yyyy 1111 0100
YF4
R/W Address
Recognition
#,ADRM26-20,A2EN,ADRM16-10,AEN
Table 132 - Master Control Register (R/W) Address (Y0X) Summary (E1)