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參數(shù)資料
| 型號(hào)： | MD80C32E-30SC |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 30 MHz, MICROCONTROLLER, CDIP40 |
| 封裝： | 0.600 INCH, CERAMIC, DIP-40 |
| 文件頁(yè)數(shù)： | 295/336頁(yè) |
| 文件大?。?/td> | 8801K |
| 代理商： | MD80C32E-30SC |
61
ATmega16M1/32M1/64M1 [DATASHEET]
8209E–AVR–11/2012
13.2
Ports as general digital I/O
The ports are bi-directional I/O ports with optional internal pull-ups. Figure 13-2 shows a functional description of
one I/O-port pin, here generically called Pxn.
Figure 13-2. General digital I/O
Note:
1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk
I/O, SLEEP, and PUD are
common to all ports.
13.2.1
Configuring the pin
Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in “Register description” on
page 78, the DDxn bits are accessed at the DDRx I/O address, the PORTxn bits at the PORTx I/O address, and
the PINxn bits at the PINx I/O address.
The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one, Pxn is configured
as an output pin. If DDxn is written logic zero, Pxn is configured as an input pin.
If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is activated. To switch
the pull-up resistor off, PORTxn has to be written logic zero or the pin has to be configured as an output pin.
The port pins are tri-stated when reset condition becomes active, even if no clocks are running.
If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If
PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero).
clk
RPx
RRx
RDx
WDx
PUD
SYNCHRONIZER
WDx: WRITE DDRx
WRx: WRITE PORTx
RRx:
READ PORTx REGISTER
RPx:
READ PORTx PIN
PUD: PULLUP DISABLE
clk
I/O : I/O CLOCK
RDx:
READ DDRx
D
L
Q
RESET
Q
D
Q
D
CLR
PORTxn
Q
D
CLR
DDxn
PINxn
D
ATA
B
U
S
SLEEP
SLEEP: SLEEP CONTROL
Pxn
I/O
WPx
0
1
WRx
WPx: WRITE PINx REGISTER
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