參數(shù)資料
型號(hào)： MCF5484CZP200
廠(chǎng)商： MOTOROLA INC
元件分類(lèi)： 微控制器/微處理器
英文描述： 32-BIT, 200 MHz, RISC PROCESSOR, PBGA388
封裝： 27 X 27 MM, 1 MM PITCH, PLASTIC, MS-034AAL-1, BGA-388
文件頁(yè)數(shù)： 26/96頁(yè)
文件大?。?/td> 2006K
代理商： MCF5484CZP200
32
MCF548x Integrated Microprocessor Hardware Specifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Signal Description
1.5.1.3
PCI Controller Signals
1.5.1.3.1
PCI Address/Data Bus (PCIAD[31:0])
The PCIAD[31:0] lines are a time-multiplexed address data bus. The address is presented on the bus during
the address phase while the data is presented on the bus during one or more data phases.
If the FlexBus is used in 32-bit address/32-bit data non-multiplexed mode, PCIAD[31:0] are used as a 32-bit
address for FlexBus transfers.
1.5.1.3.2
Command/Byte Enables (PCICXBE[3:0])
The PCICXBE[3:0] lines are time multiplexed. The PCI command is presented during the address phase
and the byte enables are presented during the data phase.
1.5.1.3.3
Device Select (PCIDEVSEL)
The PCIDEVSEL signal is asserted active low when the MCF548x decodes that it is the target of a PCI
transaction from the address presented on the PCI bus during the address phase.
1.5.1.3.4
Frame (PCIFRM)
The PCIFRM signal is asserted by a PCI initiator to indicate the beginning of a transaction. It is negated
when the initiator is ready to complete the final data phase.
1.5.1.3.5
Initialization Device Select (PCIIDSEL)
The PCIIDSEL signal is asserted during a PCI type-0 configuration cycle to address the PCI configuration
header.
1.5.1.3.6
Initiator Ready (PCIIRDY)
The PCIIRDY signal is asserted to indicate that the PCI initiator is ready to transfer data. During a write
operation, assertion indicates that the master is driving valid data on the bus. During a read operation,
assertion indicates that the master is ready to accept data.
1.5.1.3.7
Parity (PCIPAR)
The PCIPAR signal indicates the parity of data on the PCIAD[31:0] and PCICXBE[3:0] lines.
1.5.1.3.8
Parity Error (PCIPERR)
The PCIPERR signal is asserted when a data phase parity error is detected if enabled.
1.5.1.3.9
Reset (PCIRESET)
The PCIRESET signal is asserted active low by MCF548x to reset the PCI bus. This signal is asserted after
the MCF548x is reset and must be negated to enable usage of the PCI bus.
相關(guān)PDF資料
PDF描述
MCF5485CVR200 32-BIT, 200 MHz, RISC PROCESSOR, PBGA388
MCF5483CVR166 32-BIT, 166.66 MHz, RISC PROCESSOR, PBGA388
MCF5481CZP166 32-BIT, 166.66 MHz, RISC PROCESSOR, PBGA388
MCF5484CVR200 32-BIT, 200 MHz, RISC PROCESSOR, PBGA388
MCF5481CVR166 32-BIT, 166.66 MHz, RISC PROCESSOR, PBGA388
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MCF5485 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:MCF548x ColdFire㈢ Microprocessor
MCF5485CVR200 功能描述:微處理器 - MPU MCF548X V4ECORE MMU FPU RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線(xiàn)寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類(lèi)型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
MCF5485CZP200 功能描述:微處理器 - MPU MCF548X V4ECORE MMU FPU RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線(xiàn)寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類(lèi)型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
MCF548X 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:MCF548x ColdFire㈢ Microprocessor
MCF548X_07 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:MCF548x ColdFire㈢ Microprocessor
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠(chǎng)商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*