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參數(shù)資料
| 型號(hào)： | MC68HC05L16CFU |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | PLASTIC, QFP-80 |
| 文件頁(yè)數(shù)： | 135/146頁(yè) |
| 文件大?。?/td> | 852K |
| 代理商： | MC68HC05L16CFU |
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Timer 2
MC68HC05L16 MC68HC705L16 Data Sheet, Rev. 4.1
Freescale Semiconductor
89
9.3.6 Timer Input 2 (EVI)
The event input (EVI) is used as an external clock input for timer 2.
Figure 9-13. EVI Block Diagram
Since the external clock may be asynchronous to the internal clock, this input has a synchronizer which
samples external clock by the internal system clock. (The input transition synchronizes to the falling edge
of PH2. Therefore, to be measured, the minimum pulse width for EVI must be larger than one system
clock.)
The IM2 and IL2 bits in the TCR2 determine how this synchronized external clock is used. The IM2 bit
decides between event mode and gate mode, and the IL2 bit decides which level or edge is activated.
In event mode (IM2 = 0), the external clock drives the timer 2 counter directly and the active edge at the
EVI pin is selected by the IL2 bit. When an active edge is detected, the TI2F bit in the TCR2 is set.
NOTE
Since the EVI pin is shared with the PC4 I/O pin, DDRC4 should always be
cleared whenever EVI is used. EVI should not be used when DDRC4 is
high.
In gate mode (IM2 = 1), the EVI input is gated by CLK2 from the prescaler and gate output drives the timer
2 counter. The IL2 bit decides active level of the external input. When the transition from active level to
inactive level is detected, the TI2F bit is set.
Changing the IM2 bit may cause an illegal count up of TCNT2, thus presetting TCNT2 after initializing IM2
is required.
Table 9-3. EVI Modes Selection
IM2
IL2
Action on Clock
0
Falling edge of EVI increments counter
0
1
Rising edge of EVI increments counter
1
0
Low level on EVI enables counting
1
High level on EVI enables counting
PC4
EVI
SYNC
ACTIVE
EDGE/LEVEL
SELECTOR
GATE/EVENT
MODE
CONTROL
PC4
PH2
IL2
IM2
CLK2
TO TI2F
EXCLK
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