參數(shù)資料
型號： MC68HC05E16CFU
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 16256 bytes of user ROM, 320bytes of EPROM and 352 bytes of RAM
中文描述： 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP64
封裝： QFP-64
文件頁數(shù)： 42/96頁
文件大?。?/td> 3045K
代理商： MC68HC05E16CFU
MC68HC05SR3
Freescale
6-1
TIMER
6
TIMER
This section describes the operation of the 8-bit count-down timer in the MC68HC05SR3.
6.1
Timer Overview
The MC68HC05SR3 timer block diagram is shown in Figure 6-1. The timer contains a single 8-bit
software programmable count-down counter with a 7-bit software selectable prescaler. The
counter may be preset under software control and decrements towards zero. When the counter
decrements to zero, the timer interrupt flag (TIF bit in Timer Control Register, TCR) is set. Once
timer interrupt flag is set, an interrupt is generated to the CPU only if the TIM bit in the TCR and
I-bit in the CCR are cleared. When a interrupt is recognized, after completion of the current
instruction, the processor proceeds to store the appropriate registers on the stack and then
fetches the timer interrupt vector from locations $1FF6 and $1FF7.
The counter continues to count after it reaches zero, allowing the software to determine the
number of internal or external clocks since the timer interrupt flag was set. The counter may be
read at any time by the processor without disturbing the count. The contents of the counter
become stable prior to the read portion of a cycle and do not change during the read. The timer
interrupt flag remains set until cleared by the software. If a write occurs before the timer interrupt
is served, the interrupt is lost. The timer interrupt flag may also be used as a scanned status bit in
a non-interrupt mode of operation.
The prescaler is a 7-bit divider which is used to extend the maximum length of the timer. Bit 0, 1,
2 (PR0, PR1, PR2) of TCR are programmed to choose the appropriate prescaler output which is
used as the 8-bit counter clock input. The processor cannot write into or read from the prescaler;
however, its contents can be cleared to all zeros by writing to the PRER bit in the TCR. This will
allow for truncation-free counting.
The input clock for the timer sub-system is selectable from internal, external, or a combination of
internal and external sources. The TCEX and TINE bits in the Timer Control Register selects the
timer input clock.
TPG
45
05SR3.Book Page 1 Thursday, August 4, 2005 1:08 PM
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