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  • 參數資料
    型號: MC68332GMEH20
    廠商: FREESCALE SEMICONDUCTOR INC
    元件分類: 微控制器/微處理器
    英文描述: 32-BIT, 20 MHz, MICROCONTROLLER, PQFP132
    封裝: 0.950 X 0.950 INCH, 0.025 INCH PITCH, PLASTIC, ROHS COMPLIANT, QFP-132
    文件頁數: 67/109頁
    文件大?。?/td> 787K
    代理商: MC68332GMEH20
    MOTOROLA
    MC68332
    60
    MC68332TS/D
    EMU — Emulation Control
    In emulation mode, the TPU executes microinstructions from MCU TPURAM exclusively. Access to the
    TPURAM module through the IMB by a host is blocked, and the TPURAM module is dedicated for use
    by the TPU. After reset, this bit can be written only once.
    0 = TPU and TPURAM not in emulation mode
    1 = TPU and TPURAM in emulation mode
    T2CG — TCR2 Clock/Gate Control
    When the T2CG bit is set, the external TCR2 pin functions as a gate of the DIV8 clock (the TPU system
    clock divided by 8). In this case, when the external TCR2 pin is low, the DIV8 clock is blocked, prevent-
    ing it from incrementing TCR2. When the external TCR2 pin is high, TCR2 is incremented at the fre-
    quency of the DIV8 clock. When T2CG is cleared, an external clock from the TCR2 pin, which has been
    synchronized and fed through a digital filter, increments TCR2.
    0 = TCR2 pin used as clock source for TCR2
    1 = TCR2 pin used as gate of DIV8 clock for TCR2
    STF — Stop Flag
    0 = TPU operating
    1 = TPU stopped (STOP bit has been asserted)
    SUPV — Supervisor Data Space
    0 = Assignable registers are unrestricted (FC2 is ignored)
    1 = Assignable registers are restricted (FC2 is decoded)
    PSCK — Prescaler Clock
    0 = System clock/32 is input to TCR1 prescaler
    1 = System clock/4 is input to TCR1 prescaler
    IARB — Interrupt Arbitration Identification Number
    The IARB field is used to arbitrate between simultaneous interrupt requests of the same priority. Each
    module that can generate interrupt requests must be assigned a unique, non-zero IARB field value. Re-
    fer to the 3.8 Interrupts for more information.
    CIRL — Channel Interrupt Request Level
    The interrupt request level for all channels is specified by this 3-bit encoded field. Level seven for this
    field indicates a nonmaskable interrupt; level zero indicates that all channel interrupts are disabled.
    CIBV — Channel Interrupt Base Vector
    The TPU is assigned 16 unique interrupt vector numbers, one vector number for each channel. The
    CIBV field specifies the most significant nibble of all 16 TPU channel interrupt vector numbers. The low-
    er nibble of the TPU interrupt vector number is determined by the channel number on which the interrupt
    occurs.
    TICR — TPU Interrupt Configuration Register
    $YFFE08
    15
    11
    10
    8
    7
    4
    3
    0
    NOT USED
    CIRL
    CIBV
    NOT USED
    RESET:
    0
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    Freescale Semiconductor, Inc.
    For More Information On This Product,
    Go to: www.freescale.com
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