
MOTOROLA
ELECTRICAL CHARACTERISTICS
MC68331
A-22
USER’S MANUAL
A
Notes for Tables A–8 and A–8a:
1. All AC timing is shown with respect to 20% VDD and 70% VDD levels unless otherwise noted.
2. When the previous bus cycle is not an ECLK cycle, the address may be valid before ECLK goes low.
3. Address access time = tEcyc – tEAD – tEDSR.
4. Chip select access time = tEcyc – tECSD – tEDSR.
Table A-8 16.78 MHz ECLK Bus Timing
(VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH)
Num
Characteristic
Symbol
Min
Max
Unit
E1
ECLK Low to Address Valid2
tEAD
—60
ns
E2
ECLK Low to Address Hold
tEAH
15
—
ns
E3
ECLK Low to CS Valid (CS delay)
tECSD
—
150
ns
E4
ECLK Low to CS Hold
t
15
—
ns
E5
CS Negated Width
tECSN
30
—
ns
E6
Read Data Setup Time
tEDSR
30
—
ns
E7
Read Data Hold Time
tEDHR
5—
ns
E8
ECLK Low to Data High Impedance
tEDHZ
—60
ns
E9
CS Negated to Data Hold (Read)
tECDH
0—
ns
E10
CS Negated to Data High Impedance
tECDZ
—1
tcyc
E11
ECLK Low to Data Valid (Write)
tEDDW
—2
tcyc
E12
ECLK Low to Data Hold (Write)
tEDHW
15
—
ns
E13
Address Access Time (Read)3
tEACC
386
—
ns
E14
Chip Select Access Time (Read)4
tEACS
296
—
ns
E15
Address Setup Time
tEAS
1/2
—
tcyc
Table A-8a 20.97 MHz ECLK Bus Timing
(VDD = 5.0 Vdc ± 5%, VSS = 0 Vdc, TA = TL to TH)
Num
Characteristic
Symbol
Min
Max
Unit
E1
ECLK Low to Address Valid2
tEAD
—48
ns
E2
ECLK Low to Address Hold
tEAH
10
—
ns
E3
ECLK Low to CS Valid (CS delay)
tECSD
—
120
ns
E4
ECLK Low to CS Hold
tECSH
10
—
ns
E5
CS Negated Width
tECSN
25
—
ns
E6
Read Data Setup Time
tEDSR
25
—
ns
E7
Read Data Hold Time
tEDHR
5—
ns
E8
ECLK Low to Data High Impedance
tEDHZ
—48
ns
E9
CS Negated to Data Hold (Read)
tECDH
0—
ns
E10
CS Negated to Data High Impedance
tECDZ
—1
tcyc
E11
ECLK Low to Data Valid (Write)
tEDDW
—2
tcyc
E12
ECLK Low to Data Hold (Write)
tEDHW
10
—
ns
E13
Address Access Time (Read)3
tEACC
308
—
ns
E14
Chip Select Access Time (Read)4
tEACS
236
—
ns
E15
Address Setup Time
tEAS
1/2
—
tcyc