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參數資料
| 型號： | MC56603AGC60 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 數字信號處理 |
| 英文描述： | 24-BIT, 60 MHz, OTHER DSP, PBGA144 |
| 封裝： | PLASTIC, BGA-144 |
| 文件頁數： | 14/97頁 |
| 文件大小： | 1080K |
| 代理商： | MC56603AGC60 |
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DSP56603A
Synchronous Serial Interface 0 (SSI0)
MOTOROLA
DSP56603A Technical Data Sheet
1-15
SC02
PC2
Input or
Output
Input or
Output
Tri-stated Serial Control Signal 2SC02 is the frame sync for both the
transmitter and receiver in Synchronous mode, and for the
transmitter only in Asynchronous mode. When configured as
an output, this signal is the internally generated frame sync
signal. When configured as an input, this signal receives an
external frame sync signal for the transmitter (and the
receiver in synchronous operation).
Port C 2
When configured as PC2, signal direction is
controlled through the PRRC. The signal can be configured
as an SSI signal SC02 through the PCRC.
This pin is electrically disconnected internally during the
Stop processing state.
SCK0
PC3
Input or
Output
Input or
Output
Tri-stated Serial ClockSCK0 is a bidirectional Schmitt-trigger input
signal providing the serial bit rate clock for the SSI. The SCK0
is a clock input or output used by both the transmitter and
receiver in Synchronous modes, or by the transmitter in
Asynchronous modes.
Although an external serial clock can be independent of and
asynchronous to the DSP system clock, it must exceed the
minimum clock cycle time of 6T (i.e., the system clock
frequency must be at least three times the external SSI clock
frequency). The SSI needs at least three DSP phases inside
each half of the serial clock.
Port C 3
When configured as PC3, signal direction is
controlled through the PRRC. The signal can be configured
as an SSI signal SCK0 through the PCRC.
This pin is electrically disconnected internally during the
Stop processing state.
SRD0
PC4
Input
Input or
Output
Tri-stated Serial Receive DataSRD0 receives serial data and transfers
the data to the SSI Receive Shift Register.
Port C 4
When configured as PC4, signal direction is
controlled through the PRRC. The signal can be configured
as an SSI signal SRD0 through the PCRC.
This pin is electrically disconnected internally during the
Stop processing state.
Table 1-8
Synchronous Serial Interface 0 (SSI0) (Continued)
Signal
Name
Signal Type
State
During
Reset
Signal Description
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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