
6-46
G2 PowerPC Core Reference Manual
For More Information On This Product,
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MOTOROLA
Page Table Search Operation
#
#
#
#
#
# Register usage:
#
r0 is saved counter
#
r1 is junk
#
r2 is pointer to pteg
#
r3 is current compare value
#-
dMiss
dCmp
hash1
hash2
-> ea that missed
-> the compare value for the va that missed
-> pointer to first hash pteg
-> pointer to second hash pteg
.csect
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tlbmiss[PR]
vec0+0x1200
tlbCeq0:
mfspr
addi
mfctr
mfspr
addi
mtctr
lwzu
cmp
bdnzf
bne
l
andi.
beq
mtctr
mfspr
mfspr
mtcrf
mtspr
tlbld
rfi
r2, hash1
r1, 0, 8
r0
r3, dCmp
r2, r2, -8
r1
r1, 8(r2)
c0, r1, r3
0, ceq1
cEq0SecHash
r1, +4(r2)
r3,r1,0x80
cEq0ChkProt
r0
r0, dMiss
r3, srr1
0x80, r3
rpa, r1
r0
# get first pointer
# load 8 for counter
# save counter
# get first compare value
# pre dec the pointer
# load counter
# get next pte
# see if found pte
# dec count br if cmp ne and if count not zero
# if not found set up second hash or exit
# load tlb entry lower-word
# check the C-bit
# if (C==0) go check protection modes
# restore counter
# get the miss address for the tlbld
# get the saved cr0 bits
# restore CR0
# set the pte
# load the dtlb
# return to executing program
ceq0:
ceq1:
ceq2:
#+
# Register usage:
#
r0 is saved counter
#
r1 is junk
#
r2 is pointer to pteg
#
r3 is current compare value
#-
cEq0SecHash:
andi.
bne
mfspr
ori
addi
addi
b
r1, r3, 0x0040
doDSI
r2, hash2
r3, r3, 0x0040
r1, 0, 8
r2, r2, -8
ceq0
# see if we have done second hash
# if so, go to DSI exception
# get the second pointer
# change the compare value
# load 8 for counter
# pre dec for update on load
# try second hash
F
Freescale Semiconductor, Inc.
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