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  • 參數(shù)資料
    型號: COP8SGR540M3
    廠商: National Semiconductor Corporation
    英文描述: 8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two Comparators and USART
    中文描述: 8位的CMOS基于ROM和OTP微控制器具有8K到32K的內(nèi)存,2個比較器和USART
    文件頁數(shù): 37/62頁
    文件大小: 913K
    代理商: COP8SGR540M3
    10.0 Interrupts
    (Continued)
    10.3.1 VIS Execution
    When the VIS instruction is executed it activates the arbitra-
    tion logic. The arbitration logic generates an even number
    between E0 and FE (E0, E2, E4, E6 etc...) depending on
    which active interrupt has the highest arbitration ranking at
    the time of the 1st cycle of VIS is executed. For example, if
    the software trap interrupt is active, FE is generated. If the
    external interrupt is active and the software trap interrupt is
    not, then FA is generated and so forth. If the only active
    interrupt is software trap, than E0 is generated. This number
    replaces the lower byte of the PC. The upper byte of the PC
    remains unchanged. The new PC is therefore pointing to the
    vector of the active interrupt with the highest arbitration
    ranking. This vector is read from program memory and
    placed into the PC which is now pointed to the 1st instruction
    of the service routine of the active interrupt with the highest
    arbitration ranking.
    Figure 26 illustrates the different steps performed by the VIS
    instruction. Figure 27 shows a flowchart for the VIS instruc-
    tion.
    The non-maskable interrupt pending flag is cleared by the
    RPND (Reset Non-Maskable Pending Bit) instruction (under
    certain conditions) and upon RESET.
    10131729
    FIGURE 26. VIS Operation
    C
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    37
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    參數(shù)描述
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